Circuit for preventing saturation of a transistor

ABSTRACT

The present invention concerns a current amplifier which is formed by a transistor, with a view to preventing oversaturation of the transistor. The transistor saturation preventing circuit, according to the invention, includes a second transistor (Q 2 ) which constitutes a current mirror circuit with respect to a first transistor (Q 1 ) forming the current amplifier, a saturation detecting element (R 1 ) connected to the second transistor (Q 2 ) to detect saturation of the first transistor (Q 1 ), and a current feedback element (D 1 ), so as to decrease the base current of the first transistor (Q 1 ).

BACKGROUND OF THE INVENTION

a) Field of the Invention

The present invention relates to an amplifier formed by a transistor. More particularly, the invention pertains to a circuit for preventing oversaturation of a transistor which forms a current amplifier.

b) Background Art

Known current amplifiers employing transistors, generally, have circuit constructions such as are shown in FIGS. 9 and 10.

The current amplifier depicted in FIG. 9 uses a PNP type transistor Q₁, which has an emitter connected to a power supply Vcc. A load L is connected between a collector of transistor Q₁ and ground. A base of the transistor Q₁ is connected to an input terminal T, so that a base current Ib₁ flows from the base of the transistor Q₁ to the input terminal T. Thus, the transistor Q₁ supplies the load L with a collector current Ic obtained by multiplying the base current Ib₁ by a current amplification factor β.

The current amplifier shown in FIG. 10 is of a type employing an NPN type transistor Q₁₁, which has its emitter grounded, and the load L is connected between a collector of the transistor Q₁₁ and the power supply Vcc. A base of the transistor Q₁₁ is connected to the input terminal T, from which a base current Ib₁₁ flows to the base of the transistor Q₁₁. The transistor Q₁₁ supplies the load L with the collector current Ic obtained by multiplying the base current Ib₁₁ by the current amplification factor β.

FIG. 11 illustrates relationships among the collector current Ic, the base current Ib and a collector-emitter voltage Vce, which are supplied by the transistor Q₁ or Q₁₁ forming the current amplifier. In the FIG. 11, the abscissa and ordinate are drawn to represent the collector-emitter voltage Vce and collector current Ic, respectively, and a particular relation is shown between those voltage Vce and current Ic in each of the transistors Q₁ and Q₁₁, in accordance with the variation of base current Ib flowing in the transistor. Further, as evident from FIG. 11, if the collector emitter voltage Vce is somewhat higher, the collector current Ic is substantially proportional to the base current Ib, but if the collector-emitter voltage Vcc becomes lower, then the same voltage Vcc is proportional to the collector current Ic in the region where a certain amount of the base current Ib flows. At this point, the voltage Vcc is a saturation voltage Vces. In the case where the transistor Q ₁ or Q₁₁ is saturated by supplying a sufficient amount of base current Ib, the collector current Ic, the saturation voltage Vces and ambient temperature Ta bear such the relationships as shown in FIG. 12.

In FIG. 12, there are depicted the relationships between the collector current Ic and the saturation voltage Vces, with ambient temperature Ta varied, wherein the abscissa represents the collector current Ic and the ordinate the saturation voltage Vces. As is apparent from FIG. 12, the saturation voltage Vces is in direct proportion to the collector current Ic and has a positive temperature characteristic, and hence the resistance between the collector and emitter of the transistor in the saturated state is equivalent to a resistor Rces which has a positive temperature coefficient.

In the current amplifiers shown in FIGS. 9 and 10, when the transistors Q₁ and Q₁₁ are in the saturated state, a further increase of the base current Ib will make the transistors Q₁ and Q₁₁ oversaturated, rendering unstable their operations of current amplifiers. Also, the current amplifiers will similarly become unstable in operation when the internal impedance of the load L increases abruptly or a voltage is induced in the load L by an external factor.

Therefore, oversaturation of transistors must be prevented. This could be achieved by detecting the moment when the transistor is saturated, through utilization of its saturated voltage and then keeping the base current Ib from leaving or entering the base of the transistor in excess of the base current Ib which left (in the case of the PNP type transistor Q₁) or entered (in the case of the NPN type transistor Q₁₁) the base of the transistor at the moment of its saturation.

It is not easy, however, to detect the saturated state of the transistor by the saturation voltage Vces. The reason for this is that the saturation voltage Vces is influenced by the collector current Ic and ambient temperature Ta as will be seen from FIG. 12 and undergoes substantial changes according to various conditions.

OBJECT AND SUMMARY OF THE INVENTION

The present invention has for a primary object the provision of a transistor saturation preventing circuit for preventing the saturation of a transistor under any circumstances, which merely requires adding a simple circuit to a current amplifier.

To attain the above object, the transistor saturation preventing circuit according to the present invention is provided with: a current amplifier including a first transistor, a second transistor forming a current mirror circuit with respect to the first transistor, and a saturation detecting means connected to the second transistor to detect a saturation of the first transistor; and a current feedback means which, when the saturation detecting means detects the saturation of the first transistor, becomes electrically conductive, with decrease of voltage down to a level substantially equal to a base-emitter voltage of the second transistor, and feeds back at least one portion of output current of the first transistor to a state preceding the saturation detecting means of the current amplifier, thereby reducing the base current of the first transistor.

Accordingly, in such arrangement, there flows a current proportional to a collector current flowing in the first transistor, and the current flows in the second transistor which forms the current mirror circuit and saturation detecting means. Thus, detecting such current by the saturation detecting means permits for detection of saturation in the first transistor. If the saturation of the first transistor is detected by the saturation detecting means, the feedback means becomes electrically conductive, with decrease of voltage down to a level substantially equal to the base-emitter voltage of the second transistor, thereby feeding back one portion of the output current of first transistor to a circuit preceding the saturation detecting means of the current amplifier, whereby the base current of the first transistor is decreased. It is therefore possible to prevent oversaturation of the first transistor. Furthermore, the present invention ensures prevention of oversaturation of transistors in any case, and hence offers a transistor circuit which is stable regardless of input and load conditions. According to the invention, the circuit to be added therein is relatively simple and economical. In another aspect of the invention, there is employed a current mirror circuit, which serves to keep constant a current ratio between the current flowing in the first transistor and the current flowing in the saturation detecting means. Accordingly, the precision in detecting the saturation is far improved, thus preventing, more positively, the transistor against saturation. Even an excessive operation for such saturation block will not lower the efficiency of the power supply in the circuit.

For better understanding of the present invention, reference is made to the following description and accompanying drawings while the scope of the invention will be pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating an embodiment of the transistor saturation preventing circuit according to the present invention;

FIG. 2 is a circuit diagram illustrating a second embodiment of the present invention;

FIG. 3 is a circuit diagram illustrating a third embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating a fourth embodiment of the present invention;

FIG. 5 is a circuit diagram illustrating a fifth embodiment of the present invention;

FIG. 6 is a circuit diagram illustrating a sixth embodiment of the present invention;

FIG. 7 is a circuit diagram illustrating a seventh embodiment of the present invention;

FIG. 8 is a circuit diagram illustrating a eighth embodiment of the present invention;

FIG. 9 is a circuit diagram showing a conventional current amplifier;

FIG. 10 is a circuit diagram showing another conventional current amplifier;

FIG. 11 is a graph showing the relationship between the collector-emitter voltage and collector current of an ordinary transistor; and

FIG. 12 is a graph showing the temperature dependence of the collector current and the collector-emitter saturation voltage of the ordinary transistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS AND BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 illustrates a first embodiment of the transistor saturation preventing circuit according to the present invention.

The illustrated transistor saturation preventing circuit constitutes a current amplifier, wherein a transistor Q₂ is added to the conventional circuit shown in FIG. 9 which includes the transistor Q₁, forming a current mirror circuit to keep constant the input-output current ratio Ic₁ /Ir₁. In other words, in such circuit, a current flows in the second transistor Q₂ of PNP type in the same way as the collector current Ic flows in the first transistor Q₁ of the same PNP type, just as if it was reflected in a mirror, whereupon the PNP-type second transistor Q₂ constitutes a current mirror circuit of the PNP-type first transistor Q₁. The transistors Q₁ and Q₂ have their emitters connected to the power supply Vcc and have their bases connected to each other. The transistor Q₁ has its base further connected to the collector of the transistor Q₂. The load L is connected between the collector of transistor Q₁ and the ground GND. The transistor Q₂, which forms the foregoing current mirror circuit, is connected at its collector to an input terminal Ti via a resistor R₁. The resistor R₁ is set to have a minimum value of the collector-emitter voltage Vce of transistor Q₁, thus forming a saturation detecting means. The collector of transistor Q₁ is further connected to the anode of a diode D₁, which has a cathode connected to the circuit on the input terminal Ti side. With such arrangement, when the collector-emitter voltage Vce of the transistor Q₁ becomes nearly equal to the value defined by the resistor R₁, the diode D₁ is energized, thereby feeding back a portion of the collector current Ic₁ to the input-terminal-Ti-side circuit disposed at the circuit preceding the resistor R₁.

The transistors Q₁ and Q₂ form a current mirror circuit and also form a current amplifier. The resistor R₁ constitutes a saturation detecting means for detecting saturation of the transistor Q₁. The diode D₁ serves as a current feedback means. Therefore, when the transistor Q₁ becomes saturated, the transistor Q₂ equivalently acts as a mirror of the transistor Q₁, and consequently, a voltage equal to the saturation voltage Vces of the transistor Q₁ is induced in the resistor R₁, causing the diode D₁ to conduct. Such conduction of diode D₁ feeds back a portion of the output current Ic₁ of the transistor Q₁ to the input-terminal-Ti-side circuit at the circuit preceding the resistor R₁, so as to decrease the base current Ib which flows out of the transistor Q₁. At this point, between both terminals of diode D₁, there is developed a voltage drop substantially equal to the base-emitter voltage Vbe of the transistor Q₂.

In FIG. 1, an input current via the input terminal Ti is indicated by Iin; a current flowing through the resistor R₁ is indicated by Ir₁ ; the collector current of transistor Q₁ is indicated by Ic₁ ; and a current flowing through the load L is indicated by I_(L).

Now, if the input current Iin is gradually increased from zero, a potential at the side of cathode of diode D₁, which is initially equal to the supply voltage value of power supply Vcc when the input current Iin is zero, starts to drop toward the ground level by the reason that the base-emitter voltage Vbe of transistor Q₂ is induced with such increase of input current Iin and a voltage drops at the resistor R₁. At the same time, a potential at the side of anode of the diode D₁ (i.e. a potential applied to the load L), which is initially equal to the ground level when the input current Iin is zero, goes up toward the voltage of power supply Vcc in accordance with the increase of load current I_(L). Thus, the cathode-side potential of diode D₁ starts to drop from the supply voltage of power supply Vcc toward the ground level, while the anode-side potential of same D₁ is being increased, and subsequently both cathode-and anode-side potentials of diode D₁ become equal to each other. Thereafter, if the anode-side potential of diode D₁ becomes higher than its cathode-side potential, with a forward voltage applied to the diode D₁, then the diode D₁ is energized to feed back a portion of the collector current Ic₁ of transistor Q₁ to the input-terminal-Ti-side portion is added to the input current Iin. By virtue of such fed-back current, the current Ir1 will not increase any longer even if the input current Iin increases further, and circuit, whereby the thus fed-back collector current consequently, the load current I_(L) does not increase, so that the collector-emitter voltage Vce of transistor Q₁ is fixed to a certain value. Letting, now, the collector-emitter voltage of the transistor Q₁ at this point of time (when the collector-emitter voltage Vce of the transistor Q₁ is fixed to a certain value) be represented by Vce₁, and letting the base-emitter voltage of transistor Q₂ and the voltage across the diode D₁ at that time be represented by Vbe₂ and Vf₁, respectively, we can express the relation among those voltages by the following equation:

    Vce.sub.1 =Vbe.sub.2 +R.sub.1 ·Ir.sub.1 -Vf.sub.1 (1)

The transistors Q₁ and Q₂ and the diode D₁, insofar as they have the same semiconductor structure, are substantially identical in terms of forward voltage drop, including the temperature characteristic thereof, and thus, setting Vbe₂ =Vf₁, then the Eq. (1) becomes as follows:

    Vce.sub.1 =R.sub.1 ·Ir.sub.1                      (2)

Here, if it is desired to operate the transistor Q₁ until it verges very close to saturation, let the saturation voltage of transistor Q₁ be taken to be Vces₁, then it follows from the Eq. (2) that;

    Vces.sub.1 =R.sub.1 ·Ir.sub.1                     (3)

Furthermore, the resistance between the collector and emitter of the transistor Q₁ in the saturated state is equivalent to a resistor as referred to previously in FIG. 12; hence, designating Rces₁ to the equivalent resistance between the collector and emitter of transistor Q₁, the following equation can be obtained:

    Vces.sub.1 =Rces.sub.1 ·Ic.sub.1                  (4)

Substitution of the Eq. (4) into the Eq. (3) gives:

    R.sub.1 ·Ir.sub.1 =Rces.sub.1 ·Ic.sub.1

    R.sub.1 =(Ic.sub.1 /Ir.sub.1)·Rces.sub.1          (5)

The ratio (Ic₁ /Ir₁) in the Eq. (5) is the input-output current ratio of the current mirror circuit formed by the transistors Q₁ and Q₂, and this ratio can be regarded as a fixed constant which is determined by the performance of the transistors Q₁, Q₂ and values of them set in the circuit. Hence, if the value and temperature coefficient of the equivalent resistance Rces₁ are known, the set value of resistor R₁ can be determined. That is, the resistance value of resistor R₁ as the saturation detecting means corresponds to a product obtained by multiplying the proportional constant Rces₁ between the output current Ic₁ and saturation voltage Vces₁ of first transistor Q₁ by the input-output current ratio (Ic₁ /Ir₁ : current gain) of current mirror circuit composed of the transistors Q₁ and Q₂. This is expressed by the foregoing Eq. (5).

By setting the value and temperature coefficient of the resistor R₁ as described above, it is possible to prevent the transistor Q₁ from oversaturation, irrespective of the collector current Ic₁ and ambient temperature Ta. Moreover, adjusting the resistor R₁ enables desired choice of the saturation degree, including the non-saturated state.

Further, should the collector potential of transistor Q₁ go up abruptly owing to a sudden increase in the internal impedance of load L or owing to an abnormal voltage being generated by an external factor, the current flow through diode D₁ to thereby immediately cut off the base current of transistor Q₁, thus assuring to prevent the oversaturation of transistor Q₁.

FIG. 2 illustrates a second embodiment of the present invention, in which first and second transistors Q₁₁ and Q₁₂ are both NPN-type transistors. Both emitters of the transistors Q₁₁ and Q₁₂ are grounded. The transistors Q₁₁ and Q₁₂ have their bases connected to each other, with the base of the transistor Q₁₁ being connected to the collector of the transistor Q₁₂. The collector of the transistor Q₁₂ is connected to the input terminal Ti via a resistor R₁₁. The anode of a diode D₁₁ is connected to the input terminal Ti, while the cathode of the same D₁₁ is connected to the collector of the transistor Q₁₁. The load L is disposed between and connected with the power supply Vcc and the collector of transistor Q₁₁.

The second embodiment as constructed above is exactly identical to the embodiment in FIG. 1, except that the transistors Q₁₁, Q₁₂ and diode D₁₁ in the former are opposite in polarity to those in the latter, and that the application of power source voltage in this particular second embodiment differs from that in the first embodiment, which makes reversed the current direction between the two embodiments. The principle of operation and operational effect of the second embodiment are the same as those of the FIG. 1 embodiment, and a specific explanation is deleted thereon. It should be noted, however, that the resistor R₁₁ is a saturation detecting means and the diode D₁₁ is a current feedback means.

FIG. 3 illustrates a third embodiment of the present invention, which employs a PNP-type transistor Q₃ and a current mirror circuit M₁, instead of using the diode D₁ as the feedback means in the FIG. 1 embodiment. In the present embodiment of FIG. 3, the current mirror circuit M₁ is disposed between and connected with the collector of transistor Q₃ and the ground GND, with a current mirror circuit M₂ being connected to the input side (the preceding side) of the resistor R₁ which serves as saturation detecting means. Namely, the current mirror circuit M₁ is composed of NPN-type transistors Q_(M11) and Q_(M12), which have their emitters grounded. Both bases of the transistors Q_(M11) and Q_(M12) are connected to each other. The base of transistor Q_(M12) is connected to the collector of the transistor Q_(M11). Those transistors are connected to the collector of transistor Q₃. The transistor Q_(M12) has its collector connected to the input terminal Ti. The current mirror circuit M₂ is comprised of NPN-type transistors Q_(M21) and Q_(M22), which have their emitter grounded. The bases of those transistors Q_(M21) and Q_(M22) are connected to each other. The base of the transistor Q_(M21) is connected to the collector of the transistor Q_(M22). Those transistors are connected to the input terminal Ti. The transistor Q_(M21) is connected at its collector to the resistor R₁ and the base of transistor Q₃.

Now, let it be assumed that the input current to the current mirror circuit M₂ via the input terminal Ti is increased gradually from zero. Then, the collector current of the transistor Q_(M21) in the current mirror circuit M₂, which is initially zero when the input current is zero, will go up with increase of that input current to the current mirror circuit M₂. Here, since the collector current of the transistor Q_(M21) is the input current Iin, it is seen that the latter Iin increases, which induces the base-emitter voltage Vbe₂ of transistor Q₂ and also increases the voltage drop across the resistor R₁. Consequently, the base potential of the transistor Q₃, which is initially equal to the voltage of power supply Vcc when the input current to the current mirror circuit M₂ is zero, begins to drop toward the ground level, with increase of that input current to the current mirror circuit M₂. At the same time, the emitter potential of the transistor Q₃, which is initially equal to the ground level when the input current to the current mirror circuit M₂ is zero, rises toward the voltage of power supply Vcc from the ground level with an increase of the load current I_(L) as the input current to the current mirror circuit M₂ increases. Subsequently, the base potential of transistor Q₃ becomes equal to the emitter potential of the same. Thereafter, when the base potential of transistor Q₃ becomes lower than the emitter potential and the base-emitter voltage Vbe of the transistor Q₃ becomes a forward voltage, the transistor Q₃ becomes conductive. Upon the transistor Q₃ being conductive, a portion of the collector current Ic₁ is fed back to the input current of current mirror circuit M₂ via the collectors of transistors Q_(M11) and Q_(M12) in the current mirror circuit M₁. This decreases the input current to the current mirror circuit M₂. In this respect however, any further increase of such input current, which flows from the input terminal Ti to the circuit M₂, will keep the forward voltage to be applied to the transistor Q₃ and thus will not raise the input current Iin and not raise the load current I.sub. L either. In this way, the collector-emitter voltage Vce of the transistor Q₁ is fixed to a certain value. At this point, letting now the collector-emitter voltage of transistor Q₁ and the base-emitter voltage of transistor Q₃ be represented by Vce₁ and Vbe₃, respectively, we can express the relation between those two voltages as follows:

    Vce.sub.1 =Vbe.sub.2 +R.sub.1 ·Ir.sub.1 -Vbe.sub.3(6)

Also, in this embodiment, insofar as the transistors Q₂ and Q₃ have the same semiconductor structure, their respective base-emitter voltages Vbe₂ and Vbe₃, including their temperature characteristics, are substantially equal to each other (on the understanding that the transistor Q₁ is also of the same semiconductor structure as those of the foregoing two transistors). Hence, given the condition: Vbe₂ =Vbe₃, we can transform the Eq. (6) to: Vce₁ =R₁ ·Ir₁, whereupon all the other Eqs. (2) to (5) hold as similar to the embodiment in FIG. 1. Accordingly, oversaturation of the transistor Q₁ can be prevented in any cases. Further, the degree of saturation of the transistor Q₁ can be chosen arbitrarily by setting the value of the resistor R₁.

FIG. 4 illustrates a fourth embodiment of the present invention. This embodiment greatly differs from the FIG. 3 embodiment in that the first and second transistors Q₁₁, Q₁₂ and the transistor Q₃ used as feedback means are all formed by NPN-type transistors and that current mirror circuits M₁₁ and M₁₂ are both formed by PNP-type transistors. Specifically, the transistors Q₁₁ and Q₁₂ have their emitters grounded, and have their bases connected to each other, wherein the base of transistor Q₁₁ is connected to the collector of transistor Q₁₂. The collector of the transistor Q₁₂ is connected via a resistor R₁₂ to the current mirror circuit M₁₂. The load L is disposed between and connected with the power supply Vcc and collector of the transistor Q₁₁. The base of transistor Q₁₃ is connected to the point where the resistor R₁₂ and current mirror circuit M₁₂ are connected together, whereas the collector of the transistor Q₁₃ is connected to the current mirror circuit M₁₁ and the emitter of the same Q₁₃ is connected to the collector of transistor Q₁₁. The current mirror circuit M₁₁ is comprised of PNP-type transistors Q_(M111) and Q_(M112), which have their emitters connected to the power supply Vcc. The bases of the transistors Q_(M111) and Q_(M112) are connected to each other, wherein the base of the transistor Q_(M112) is connected to the collector of the transistor Q_(M111), and those transistors arc connected to the collector of the transistor Q₁₃. The transistor Q_(M112) has its collector connected to the input terminal Ti. The current mirror circuit M₁₂ is comprised of PNP-type transistors Q_(M121) and Q_(M122), the emitters of which are connected to the power supply Vcc. The bases of the transistors Q_(M121) and Q_(M122) are connected to each other, wherein the base of transistor Q_(M121) is connected to the collector of transistor Q_(M122), and hence both transistors are connected to the input terminal Ti. The collector of transistor Q_(M112) is connected to the base of the transistor Q₁₃ and to the collector of the transistor Q₁₂ via the resistor R₁₂.

The present embodiment in FIG. 4 is exactly identical in construction to the FIG. 3 embodiment above, except that the transistors Q₁₁, Q₁₂, Q₁₃ and current mirror circuits M₁₁ and M₁₂ in the former embodiment are opposite in polarity to those in the latter embodiment, and except that the application of power source voltage in this particular fourth embodiment differs from that in the third embodiment, which makes reversed the current direction between the two embodiments. The principle of operation and operational effect of this embodiment are the same as those of the FIG. 3 embodiment, and hence will not be described in detail. It is noted here that the resistor R₁₂ constitutes a saturation detecting means and designations M₁₁ and M₁₂ denote the current mirror circuits.

FIG. 5 illustrates a fifth embodiment of the present invention. This embodiment is constructed, using the FIG. 1 embodiment, such that the load L is connected via a power transistor Q₀ to the first embodiment, so as to increase the output current capacity, forming an emitter-follower current amplifier. The transistor Q₁ is connected at its collector to the base of the power transistor Q₀. The collector of this power transistor Q₀ is connected to the power supply Vcc. The load L is disposed between and connected with the emitter of power transistor Q₀ and the ground GND.

The principle of operation and operational effect of this fifth embodiment are exactly identical with those of the FIG. 1 embodiment, except that a large current can be applied to the load L by the power transistor Q₀.

FIG. 6 illustrates a sixth embodiment of the present invention. This embodiment is constructed, using the second embodiment in FIG. 2, such that the load L is connected to that second embodiment via an PNP-type power transistor Q₀₁, which thus forms an emitter-follower current amplifier. specifically, according to this FIG. 6 embodiment, the collector of the transistor Q₁₁ is connected to the base of the power transistor Q₀₁. The collector of that power transistor Q₀₁, is grounded, and the emitter of the same Q₀₁ is connected via the load L to the power supply Vcc. The principle of operation and operational effect in the present embodiment are the same as those of the FIG. 5 embodiment, and hence no detailed description thereof will be repeated.

FIG. 7 illustrates a seventh embodiment of the present invention. In this embodiment, a transistor Q₄ is employed as a saturation detecting means, in place of the resistor R1 which is used as the saturation detecting means in the FIG. 3 embodiment, and further there is employed a current mirror circuit M₃ comprising three transistors Q_(M31), Q_(M32) and Q_(M33), in place of the current mirror circuit M₂ including the two transistors Q_(M21), and Q_(M22) in the FIG. 3 embodiment. The collector of the transistor Q_(M33) in the current mirror circuit M₃ is connected to the input terminal Ti of the current circuit of this embodiment. The collector of another transistor Q_(M32) in the current mirror circuit M₃ is connected to the base of the transistor Q₄. The collector of still another transistor Q_(M33) in the current mirror circuit M₃ is connected to the collector of transistor Q₄ as well as to the base of transistor Q₃.

Now, let it be assumed that the input current to the current mirror circuit M₃ from the input terminal Ti is increased gradually from zero. The collector current of the transistor Q_(M12), is still zero, and thus, with regard to the collector current (equal to the current Iin) of the transistor Q_(M31) in the current mirror circuit M₃, the initial zero level of the collector current, when the input current thereto is zero, increases with an increase of the collector current (equal to the input current) of the other transistor Q_(M33) in the same circuit M₃. At the same time, the collector current (equal to the base current Ib₄ of the transistor Q₄) of the transistor Q_(M32) is similarly increased in the same circuit M₃. Suppose that the current ratio, Ib₄ /Iin, in that current mirror circuit M₃ is set at such a value that renders the transistor Q₄ completely saturated. Then, the collector-emitter voltage Vce of transistor Q₄ becomes a saturation voltage Vces₄ that increases in proportion to a collector current Ic₄ of the transistor Q₄. When the current Iin increases from zero as mentioned above, the base potential of the transistor Q₃ starts to drop toward the ground level from the supply voltage Vcc, owing to the saturation voltage Vces₄ and the base-emitter voltage Vbe₂ of the transistor Q₂. At the same time, the emitter potential of the transistor Q₃ rises toward the supply voltage Vcc from the ground level with an increase of the load current I_(L). Then, when the base potential of transistor Q₃ drops lower than the emitter potential thereof, the base-emitter voltage Vbe₃ in the same transistor Q₃ becomes a forward voltage. Thus, the transistor Q₃ conducts, feeding back a portion of the collector current Ic₁ to the collector of transistor Q_(M33) of the current mirror circuit M₃, via the base of the transistor Q_(M11) and collector of the transistor Q_(M12) of the current mirror circuit M₁. With such feedback of current, any further increase of the input current, which flows from the input terminal Ti to the current mirror circuit M.sub. 3, will not lead to increase of current Iin, as explained in the foregoing embodiment in FIG. 3. Accordingly, the load current I_(L) will not increase either. In this way, the collector-emitter voltage Vce of the transistor Q₁ is fixed to a certain value. The collector-emitter voltage Vce₁ of the transistor Q₁ at this moment can be obtained by the following equation:

    Vce.sub.1 =Vbe.sub.2 +V.sub.ces.sub.4 -Vbe.sub.3           (7)

Also in this embodiment, insofar as the transistors Q₂ and Q₃ have the same semiconductor structure, their respective base-emitter voltages Vbe₂ and Vbe₃, including their temperature characteristics, are substantially equal to each other (on the understanding that the transistor Q₁ is also of the same semiconductor structure as those of the foregoing two transistors). Hence, given the condition: Vbe₂ =Vbe₃, we can transform the Eq. (7) above to:

    Vce.sub.1 =Vces.sub.4                                      (8)

Here, let us give Rces₄ to the equivalent resistance between the collector and emitter of transistor Q₄ in saturated state. Then, Eq. (8) becomes as follows:

    Vce.sub.1 =Rces.sub.4 ·Ic.sub.4                   (9)

Similar to the embodiments in FIGS. 1 through 4, the following equations may be established: ##EQU1##

    Rces.sub.4 =(Ic.sub.1 /Ic.sub.4)·Rces.sub.1       (11)

The ratio (Ic₁ /Ic₄) in the Eq. (11) is the input-output current ratio of the current amplifier composed of the transistors Q₁ and Q₂ ; namely, a current gain. Therefore, the resistance Rces₄ may be multiplied by the current gain (Ic₁ /Ic₄) of the resistance Rces₁. If the transistors Q₁, Q₂, Q₃ and Q₄ have the same semiconductor structure, there is no difference in temperature coefficient between the resistances Rces₁ and Rces₄, which eliminate the need for temperature compensation in this embodiment. The equivalent resistance between the collector and emitter of each of the transistors Q₁ and Q₄ in their saturated state can be controlled by the size of the transistor as well. Thus, this embodiment also insures prevention of oversaturation of the transistor Q₁ in any cases. Besides, the degree of saturation of the transistor Q₁ may be set selectively, depending on the size of the transistor Q₄.

FIG. 8 illustrates an eighth embodiment of the present invention. This embodiment greatly differs from the one in FIG. 7, in that the first and second transistors Q₁₁, Q₁₂ and a transistor Q₁₃ used as feedback means are all NPN-type transistors, and that there are employed current mirror circuits M₁₁ and M₁₃ which comprise PNP-type transistors. The transistors Q₁₁ and Q₁₂ have their emitters grounded. Both bases of those transistors Q₁₁, Q₁₂ are connected to each other, with the base of transistor Q₁₁ being connected to the collector of transistor Q₁₂. The collector of the transistor Q₁₂ is, in turn, connected via a transistor Q₁₄ to the current mirror circuit M₁₃. The load L is disposed between and connected with the power supply Vcc and the collector of the transistor Q₁₁. The transistor Q₁₃ is connected at its base to the point where the collector of transistor Q₄ and the current mirror circuit M₁₃ are connected together. The collector of transistor Q₁₃ is connected to the current mirror circuit M₁₁. The emitter of the same Q₁₃ is connected to the collector of transistor Q₁₁. The current mirror circuit M₁₁ is comprised of PNP-type transistors Q_(M111) and Q_(M112). Both emitters of transistors Q_(M111) and Q_(M112) are connected to the power supply Vcc. The bases of those transistors Q_(M111), Q_(M112) are connected to each other, and connected to the collector of transistor Q_(M111) ; hence, the transistors are connected to the collector of transistor Q₁₃. The transistor Q_(M112) has its collector connected to the input terminal Ti. The current mirror circuit M₁₃ is comprised of PNP-type transistors Q_(M13), Q_(M132) and Q_(M133), wherein the emitters respectively of the transistors Q_(M131), Q_(M132), Q_(M133) are connected to the power supply Vcc. All bases of the transistors Q_(M131), Q_(M132), Q_(M133) are connected with each other, and connected to the collector of the transistor M₁₃₃ ; hence the transistors are connected to the input terminal Ti. The transistor Q_(M131) has its collector connected to the base of the transistor Q₁₃ and the collector of the transistor Q₁₄. The transistor Q_(M132) has its collector connected to the base of the transistor Q₁₄. The emitter of transistor Q₁₄ is connected to the collector and base of the transistor Q₁₂.

The above-described embodiment in FIG. 8 is identical with the one in FIG. 7, except that the transistors Q₁₁, Q₁₂, Q₁₃ and the current mirror circuits M₁₁, M₁₃ in the former embodiment are opposite in polarity to those in the latter, and that the application of power source voltage in this particular eighth embodiment differs from that in the seventh embodiment, which makes reversed the current direction between the two embodiments. The principle of operation and operational effect of the present embodiment are the same as those of the FIG. 7 embodiment, and no detailed description thereon will be given. It is noted here that the transistor Q₁₄ forms a saturation detecting means.

The above-described embodiments are illustrative of preferred embodiments of the present invention, but the invention is not limited specifically thereto and various modifications and variations may be effected without departing from the scope and gist of the invention. For instance, the addition of the power transistor, as in the embodiments of FIGS. 5 and 6, may be done in the other embodiments as well. If the power transistor is added to the transistor Q₁ in the embodiments other than the ones shown in FIGS. 5 and 6, it is possible to increase the capacity of current sufficient to be supplied to the load L.

It may also be possible to combine the embodiment(s) in FIGS. 1 and/or 4 with the ones in FIGS. 7 and 8.

According to the embodiments in FIGS. 1, 2, 3, 4, 5 and 6, the degree of saturation of the transistors Q₁ and Q₁₁ is not sensitive to and not influenced by a change in the set value of the resistor R₁, so that the resistor R₁, R₁₁ need not necessarily be set at a value equal to a calculated value, but may be set close thereto. Accordingly, the value of the resistor R₁, R₁₁ can be roughly set, with ease. In the case where the circuit of the present invention is fabricated as an integrated circuit (IC), the resistor R₁, R₁₁ normally has a positive temperature coefficient close to the saturation voltage of the transistor. This saves the necessity of temperature compensation and allows ease in the design of the circuit.

The transistor saturation preventing circuit according to the present invention is applicable to electronic circuits, integrated circuits and similar circuits which amplify and supply current. Moreover, the circuit in the invention operates stably, irrespective of an input condition and a load condition, and therefore may be applied to a measuring circuit which requires intricate connection with other pertinent circuits, a protective circuit for a circuit whose load condition is changeable extremely, and the like.

While the foregoing description and drawings represent the preferred embodiments of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the true spirit and scope of the present invention. 

I claim:
 1. A transistor saturation preventing circuit, comprising a current amplifier which includes a first transistor, a second transistor which forms a current mirror circuit with respect to said first transistor, and a saturation detecting means for detecting a saturation of said first transistor; said saturation detecting means being connected to said second transistor; current feedback means which, when said saturation detecting means detects the saturation of said first transistor, becomes electrically conductive, with decrease of voltage across said current feedback means down to a level substantially equal to a base-emitter voltage of said second transistor, and feeds back at least one portion of output current of said first transistor to a circuit preceding said saturation detecting means of said current amplifier, thereby reducing a base current of said first transistor.
 2. The transistor saturation preventing circuit according to claim 1, wherein said saturation detecting means is a resistor.
 3. The transistor saturation preventing circuit according to claim 1, wherein said saturation detecting means is a transistor.
 4. The transistor saturation preventing circuit according to claim 1, wherein said current feedback means is a diode.
 5. The transistor saturation preventing circuit according to claim 1, wherein said current feedback means is a transistor.
 6. The transistor saturation preventing circuit according to claim 1, wherein said current feedback means is a current mirror circuit. 